Sarance at DesignCon
We will be showcasing a live demo of our Interlaken IP at DesignCon in Santa Clara, California at end of January 2007. The demo is done in partnership with Altera® and will be located in Altera®'s booth (#503).
The demo uses an Altera® Stratix® II GX Signal Integrity board and runs Interlaken over five 6.375Gpbs SERDES transceivers. That's a whopping 31.785Gbps of data transmitted and received by the FPGA over a single pipe! That's the same as sending and receiving an entire DVD every 1.2 seconds!!
The FPGA is programmed with Sarance's Interlaken IP and four independent packet generators and monitors. Each generator/monitor pair is capable of filling the entire bandwidth of the Interlaken pipe with Ethernet packets (header, PRBS-23 payload, and FCS) sized anywhere above 64 bytes.
A GUI is used to control all of the features of the FPGA including Interlaken parameters, generator/monitor parameters and, as a bonus, the ability to inject errors in the transmitting bit stream to demonstrate the IP's ability to detect and recover from various error conditions without requiring any external input.
We look forward to seeing you at DesignCon. If you will not be at DesignCon and want more information about our Interlaken IP and demo, send an email to interlaken@sarance.com.
