What's New

August 5, 2008 :

Sarance's 100G Ethernet IP Cores used to carry live internet traffic

• Press Release
• Sarance's 40G/100G Ethernet Products

May 8, 2008 :

Interlaken products for Xilinx Virtex 5 FXT devices with built-in gearbox

• Sarance's Interlaken Products

August 31, 2007 :

Sarance White Paper: "Scaling Chip-to-Chip Interconnect Made Simple"

• Sarance's Interlaken Products

• More News

Sarance Technologies - Interlaken IP Cores

Interlaken is a scalable chip-to-chip interconnect protocol designed to enable transmission speeds from 10Gbps to 100Gpbs and beyond.  Interlaken takes the best of existing protocols and builds a channelized protocol that operates over the currently available serial link technologies.

The channelized protocol is flexible enough to allow system designers to optimally designate different functions between multiple devices.  For example, in a typical router, one device can be used to perform aggregation and classification before passing the packets to a second device that performs traffic management.  With the channelized protocol of Interlaken, the classification information is easily transmitted to the traffic manager without much (if any) overhead.

Using a serial interface dramatically lowers the pin requirement for the chip-to-chip interface.  Compared to the SPI4.2 protocol, Interlaken requires 90% less pins.  In addition, the Interlaken protocol can be implemented using as many number of serial links as required to achieve the desired bandwidth.  This scalable approach allows a simple and straight forward migration path for system designers to implement higher performance systems: there is no need to change the chip-to-chip interconnect technology ever ! Simply scale the current Interlaken implementation by adding more serial links, and get more bandwidth.

Interlaken also improves the data integrity of the transmission link relative to other protocols.  A 67/64 bit encoding scheme along with a self-synchronizing scrambler is used to maintain proper DC balance.  Payload data integrity is monitored using a CRC24 mechanism and each serial link's integrity can be monitored using a CRC32 algorithm.

Sarance Technologies offers Intellectual Property (IP) cores implementing different configurations of Interlaken targeted at any ASIC process technology, Xilinx Virtex™-5, and Altera® Stratix® II GX FPGA devices. For more information, please click on the following links:

• Altera® FPGA Interlaken IP Cores
• Xilinx FPGA Interlaken IP Cores
• ASIC Interlaken IP Cores

Interlaken on the web:

January 24, 2007:
Sarance Interlaken IP Cores and Cortina Systems' ASICs achieve 40Gbps interoperability

January, 2007:
Live 40G Interlaken Demo at DesignCon

December 15, 2006:
Sarance Technologies Delivers Interlaken IP Core for Xilinx Virtex-5 FPGAs

August 14, 2006:
ConnectivityZONE Product Review: Altera®/Sarance IP Core for FPGAs

August 14, 2006:
Altera®, Sarance join Cortina-Cisco coalition

April 03, 2006:
Cortina Systems and Cisco Systems announce the Interlaken protocol specification

April 03, 2006:
FACE-OFF Cisco challenges interconnect industry ( also featured on EE Times )