ASIC Interlaken IP Cores
Overview
Interlaken is a scalable chip-to-chip interconnect protocol designed to enable transmission speeds from 10Gbps to 100Gpbs and beyond. Using the latest SERDES technology and a flexible protocol layer, Interlaken minimizes the pin and power overhead of chip-to-chip interconnect and provides a scalable solution that can be used throughout an entire system.
Sarance's Interlaken IP core (IIPC) is architected to take advantage of Interlaken's scalability. The IIPC is a high-performance, low-power implementation of Interlaken and is capable of transferring up to 150Gbps of bandwidth spread over any number of lanes. For example, using 10Gbps SERDES technology, the IIPC needs 15 lanes to achieve maximum throughput. Alternatively, 24 lanes are needed if 6.25Gbps SERDES technology is used.
The IIPC is available today and can be easily integrated into any ASIC design flow. It is delivered with a full suite of support structure including BFMs, testbenches, synthesis and STA constraints, CTS and clock specifications. Sarance supports both Synopsys Design Compiler® and Cadence Encounter® RTL Compiler tool flows.
Sarance Interlaken IP Cores are hardware proven to be interoperable with Cortina Systems' ASICs at 40Gbps.
Key Features
- Compliant with the Interlaken Protocol Definition, Revision 1.1
- Designed to take full advantage low-power ASIC design flows and methodology
- Automatic scaling of clocks to minimize power consumption
- Support for any serial data rate; 10Gbps, 6.25, etc.
- Flexible SERDES interface to accommodate different I/O implementations
- Data striping and de-striping across 1 to n lanes; only limited by hardware resources
- Synthesizable in any standard cell library
- Fully SCAN compliant soft macro
- Programmable BurstMax, BurstMin, BurstShort and MetaFrameSize parameters
- 64/67 encoding and decoding
- Automatic word and lane alignment
- Self-synchronizing data scrambler
- Configurable internal data bus width of 64, 128 or 256 bits
- CRC24 generation and checking for burst data integrity
- CRC32 generation and checking for lane data integrity
- Data scrambling and disparity tracking to minimize baseline wander and maintain DC balance
- Support for Synchronization, Scrambler State, Diagnostic, and Skip Word Block Types
- Programmable Rate Limiting circuitry
- Error condition detection and recovery
- Channel-level and link-level flow control mechanism