Altera® FPGA Interlaken IP Cores
Overview
Interlaken is a scalable chip-to-chip interconnect protocol designed to enable transmission speeds from 10Gbps to 100Gpbs and beyond. Using the latest SERDES technology and a flexible protocol layer, Interlaken minimizes the pin and power overhead of chip-to-chip interconnect and provides a scalable solution that can be used throughout an entire system. In addition, Interlaken uses two levels of CRC checking and a self-synchronizing data scrambler to ensure data integrity and link robustness.
Sarance᾿s Interlaken Protocol IP Core is compliant with the Interlaken Protocol Definition, Revision 1.1, and offers system designers with a risk-free and quick path for adopting Interlaken as their chip-to-chip interconnect protocol.
Sarance Interlaken IP Cores are hardware proven to be interoperable with Cortina Systems' ASICs at 40Gbps.
Key Features
- Compliant with the Interlaken Protocol Definition, Revision 1.1
- Support for up to 6.375 Gbps serial data rate
- Data striping and de-striping across 1 to 24 lanes
- Programmable BurstMax, BurstMin, BurstShort and MetaFrameSize parameters
- 64/67 encoding and decoding
- Automatic word and lane alignment
- Self-synchronizing data scrambler
- Configurable internal data bus width of 64, 128 or 256 bits
- CRC24 generation and checking for burst data integrity
- CRC32 generation and checking for lane data integrity
- Data scrambling and disparity tracking to minimize baseline wander and maintain DC balance
- Support for Synchronization, Scrambler State, Diagnostic, and Skip Word Block Types
- Programmable Rate Limiting circuitry
- Error condition detection and recovery
- Channel-level and link-level flow control mechanism
Typical Application
