IP Cores

High-Speed Interconnect

• Interlaken
• 40G/100G High-Speed Ethernet

Classification

• Network Search Engine
• CAM Core

Traffic Management

• Traffic Policing
• DDR2 SDRAM Packet Buffer

DDR-II SDRAM Packet Buffer IP Cores

Overview

To address the need for a high bandwidth yet cost effective packet buffering solution, Sarance Technologies᾿ has developed and implemented a packet buffer that is based on DDR-II SDRAM devices.  DDR-II SDRAM is widely used, and provides a cost effective alternative to other memory technologies, without suffering from any security of supply issues.  The packet buffer has been designed as a channelized core, where each core connects to a single DDRII SDRAM device and supports a worst case symmetric throughput of 2.5 Gbps.  Solutions reaching and exceeding 10G rates can be built by instantiating  parallel cores.  

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